In CMOS technology, circuits are formed that are integrated on a substrate, the circuits having n-channel field effect transistors and p-channel field effect transistors. When the transistors of different conduction types are dimensioned identically, it happens that an n-channel transistor of a CMOS circuit has a different current driver capability than a p-channel transistor of the circuit.
In the case of integrated circuit components in CMOS technology that have n-MOS transistors and p-MOS transistors (for example inverters, oscillators, etc.), the different current driver capability of the transistors of different conduction types is compensated for in accordance with the prior art by providing p-MOS transistors having a different transistor width than n-MOS transistors. A p-channel transistor having a larger (e.g., double to triple) width than the corresponding n-channel transistor is often provided.
However, increasing the transistor width of the p-channel transistor in a CMOS circuit has the disadvantage that this enlarges the area requirement for realizing the circuit on a silicon chip. Valuable silicon area is lost as a result, which is disadvantageous in view of the cost pressure in semiconductor technology.
A description is given below, referring to FIG. 1A, FIG. 1B, of an n-MOS field effect transistor 100 and a p-MOS field effect transistor 110 of a CMOS circuit in accordance with the prior art.
The n-MOS field effect transistor 100 from FIG. 1A contains a first source/drain region 101 and a second source/drain region 102, between which a channel region 103 is formed. The electrical conductivity of the channel region 103 can be controlled by means of applying an electrical voltage to a gate region 104. The transistor width of the n-MOS field effect transistor 100 is designated by d1 in FIG. 1A.
FIG. 1B shows a p-MOS field effect transistor 110, which is intended to have the same current driver capability as the n-MOS field effect transistor 100. The p-MOS field effect transistor 110 likewise has a first source/drain region 111 and a second source/drain region 112, between which a channel region 113 is formed. The electrical conductivity of the channel region 113 can be controlled by means of applying an electrical signal to a gate region 114.
As shown in FIG. 1B, the transistor width d2 of the p-MOS field effect transistor 110 is significantly greater than the transistor width d1 of the n-MOS field effect transistor 100.
The different transistor widths d1, d2 are necessary in order to achieve identical current driver capabilities of the transistors in a CMOS arrangement in which the n-MOS field effect transistor 100 and the p-MOS field effect transistor 110 are integrated. Consequently, the p-MOS field effect transistor 110 requires approximately triple the area of the n-MOS field effect transistor 100 in order to achieve the same current driver capability in both transistors 100, 110. This is disadvantageous since the necessary chip area for forming the transistors 100, 110 is thereby enlarged.
In view of the demand for increasingly smaller integrated components and transistors, which enable good control of the electrical conductivity of the channel region even with continued scaling, alternatives to conventional field effect transistors are the subject of current research and development. One such novel type of field effect transistor is the so-called fin field effect transistor. In the case of a fin field effect transistor, in a thin fin, that is to say in a thin semiconductor fin having a width of, for example, 50 nm or less, two end sections are formed as source/drain regions, a channel region being formed between the two source/drain regions in the fin. The channel region is covered by a gate insulating layer. A gate electrode is formed on the gate insulating layer, that is to say above the fin, and enables lateral driving of the electrical conductivity of the fin.
However, even in fin field effect transistors the problem arises that p-fin field effect transistors have current driver capabilities or generally transistor properties which differ from the current driver capabilities or transistor properties of an n-fin field effect transistor given identical dimensioning.
Anil, K G, et al. (2003) “Layout Density Analysis of FinFETs,” ESSDERC 2003, 16.-18.09.2003 Estoril, Portugal, discloses a fin field effect transistor arrangement in which the fins of an n-MOS fin field effect transistor and the fin of a p-MOS fin field effect transistor are divided into a plurality of semiconductor partial fins formed alongside one another, it being possible for the current driver capability of the two transistors to be coordinated with one another by virtue of a different number of partial fins in the n-MOS fin field effect transistor and in the p-MOS fin field effect transistor. However, this concept has the disadvantage that the space requirement of the transistor arrangement is increased by means of dividing the fin into a plurality of partial fins, which counteracts the endeavor to increase the integration density.
A description is given below, referring to FIG. 1C, of an n-MOS fin field effect transistor 120 and, referring to FIG. 1D, of a p-MOS fin field effect transistor 130 in accordance with the prior art in which similar current driver capabilities are sought by providing in each case a plurality of partial fins that differ in their number.
The n-MOS fin field effect transistor 120 contains two silicon partial fins 125, 126. One end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120, which are arranged parallel to one another, forms a first source/drain region 121, and another end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120, which are parallel to one another, forms a second source/drain region 122. A channel region 123 is formed between the first source/drain region 121 and the second source/drain region 122, and the conductivity of the channel region can be controlled by a gate region 124 formed on the silicon partial fins 125, 126. A gate insulating layer (not shown) is arranged between the gate region 124 and the silicon partial fins.
The p-MOS fin field effect transistor 130 contains six silicon partial fins 135. One end section of the silicon partial fins 135 of the p-MOS fin field effect transistor 130, which are parallel to one another, forms a first source/drain region 131, and another end section of the silicon partial fins 135 of the n-MOS fin field effect transistor 130, which are arranged parallel to one another, forms a second source/drain region 132. A channel region 133 is formed between the first source/drain region 131 and the second source/drain region 132, and the electrical conductivity of the channel region can be controlled by a gate region 134 formed on the silicon partial fins 135. A gate insulating layer (not shown) is arranged between the gate region 134 and the silicon partial fins 135.
As emerges from FIG. 1C, FIG. 1D, the area requirement of a field effect transistor having a plurality of partial fins is all the greater, the larger the number of partial fins. Consequently, the provision of a plurality of partial fins considerably increases the area requirement.
Furthermore, U.S. Pat. No. 6,413,802 (the '802 Patent) describes a fin field effect transistor device, in which case, in accordance with one embodiment described therein, a plurality of field effect transistors are provided, which are stacked one above another and are insulated from one another by a dielectric layer in each case. For this stack of transistors, the '802 Patent furthermore describes that the ratio of the widths of the NMOS field effect transistors and PMOS field effect transistors can be adapted by means of adapting the thicknesses of the semiconductor layers.
U.S. patent application Publication No. 2004/0023506 discloses a method for producing a gate oxide layer with two regions having a different layer thickness.
U.S. Pat. No. 4,996,574 describes a MIS field effect transistor whose channel region is significantly smaller than double the maximum propagation of the depletion region that can form in the channel region.